Binary number system converter



Sept. 11, 1956 E. w. SAMSON ErAL 2,762,563

BINARY NUMBER SYSTEM CONVERTER Original Filed Aug. lO, 1951 Imi. 2E/5 5..

(a) {He/TH) I pf2/7 Y L /lVE' (ayez/c 7a lik/7H) SYSTEM WP. @Wwf I l I d J-L r 3 d' R4 HEI THNE 7' /CHL 60A/POL CIRCUIT C YCL /C SYSTEM sym-EM United States Patent O 2,762,563 BIN ARY NUMBER SYSTEM CONVERTER Edward W. Samson, Watertown, and Edmund B. Staples, Westwood, Mass.

Original application August 10, 1951, Serial No. 241,378. Divided and this application November '5, 1952, Serial No. 318,969

2 Claims. (Cl. 23S- 61) (Granted under Title 35, U. S. Code (1952), sec. 266) The invention described herein may be manufactured and used by or for the Government for governmental purposes without payment to us of any royalty thereon.

This application is a division of application Serial Number 241,378, led August 10, 1951.

This invention relates to a converter for producing transformations between two systems of binary numbers. Specifically, it is the object of the invention to provide means for converting cyclic binary number codes into ordinary arithmetical binary number codes, or for reversing the process.

The cyclic system of binary numbers is an arrangement of the number order so as to follow a definite pattern characterized by the change of only one digit between any number and the number adjacent to it. The cyclic system may be used in mechanical commutating coding systems to eliminate any ambiguities as to mechanical position when multiple contacts or brushes are moved from one number or commutator to an adjacent one. This system of numbers is not adaptable to the ordinary arithmetical processes such as addition, multiplication, etc.

in the ordinary or arithmetical system of binary numbers a quantity is represented as the sum of powers of 2. Hence the value of any positive quantity A may be represented in accordance with this system as where n and m are positive integers and the coefficients ak and a-k are either l or depending upon whether or not the quantity 2k or 2-k appears in A. The coetlcients ak and a-k constitute the binary number and are positioned on either side of the binal point. If A is a whole quantity the coeicients a-k are all zero. Arithmetical computations can be made with this system of binary numbers.

Examples of four digit binary numbers in accordance with the above two systems are shown below: E

The converter operates on the principle that any digit in either a cyclic or arithmetical binary number is dependent only on the corresponding digit in the opposite system and the adjacent, higher-order digit in the arith- 4rnetical. If the higher-order digit is l, the transformation is a reversal (0 to 1 or 1 to 0), whereas, if the higherorder digit is 0, the transformation is without change (Oto 0 or 1 to l).

The construction and operation of converters in accordance with the invention will be more clearly understood from the specific embodiments thereof to be described in connection with the accompanying drawings in which- Figure 1 shows examples of pulse binary codes in both the cyclic and arithmetical systems;

Figure 2 shows a converter for use with series pulse codes;

Figures 3a and 3b show converters for use with pulse codes in which the pulses occur simultaneously; and

Figures 4 and 5 show suitable control circuits for use in the converters of Figures 2, 3a and 3b.

A binary number may be represented electrically as a series of pulses, usually equally spaced, occurring in a single circuit over a period of time, or as a plurality of pulses occurring simultaneously in parallel circuits. The Idigit 1 is usually represented by a positive pulse, whereas the digit 0 may be presented by a negative pulse or by the absence of a pulse. For example, in Figure l (a) four digit series pulse codes are shown representing the quantity 5 in both the cyclic and the arithmetic systems. The cyclic binary number 0111 is represented by the absence of the pulse at time t1, indicating that the first digit is 0, and the presence of pulses at t2, t3 and t4, indicating that each of the last three digits is 1. The arithmetic binary umber 0101 is represented in a similar manner.

A converter in block form for producing transformation between the two systems is shown in Figure 2. The binary number in series pulse form, to be transformed to the opposite system is applied to the digit pulse input terminal 1 and the Idigit pulses of the resulting transformation appear at the digit pulse output terminal 3.

Delay line 4 has its input connected by means of switch 6, to terminal 1 or 3 on which the digital pulse code appears. Therefore, for transforming the cyclic code to the arithmetical the switch is connected to terminal 3, whereas for the reverse transformation it is connected to terminal 1. The delay to produced by line 4 is equal to the spacing of adjacent pulses in the pulse code.

The delayed pulses from line 4 are applied to terminal 2 of control circuit 5 which is interposed between the input and output terminals 1 and 3. The output of control circuit 4 is determined by the combinations of input and control pulses applied thereto in accordance with the following tabulation in which l indicates the presence of a pulse and 0 the absence of a pulse:

The operation of the converter will be clear from a consideration of the transformation of the cyclic binary number of Figure 1.(a) to the arithmetical binary number of Figure 1(a). For this transformation switch 6 is connected to terminal 3. At time t1 there is no input pulse and no control pulse so that no output pulse occurs; at time t2 there is an input pulse but no control pulse so that an output pulse occurs; at time t3 there is an input pulse and a control pulse, derived by delaying the output pulse at t2, so mat no output pulse occurs; and at time t4 there is an input pulse but no control pulse so that an output pulse occurs. Application of a cyclic binary pulse code to input terminal 1, therefore, results in its transformation into the corresponding arithmetical binary pulse code at output terminal 3. Conversely, application of an arithmetical' binary pulse code to input terminal 1, with switch 6 connected to terminal 1, results in its transformation into the corresponding cyclic pulse code at the output terminal 3. In this case at ti there is no input or control pulse and therefore no output pulse; at t2 there is an input pulse but no control pu-lse so that an output pulse occurs; at t3 there is no input pulse but there is a control pulse, lderived by delaying the input pulse n, so that an output pulse occurs; and at t4 there is an input pulse but no control pulse so that an output pulse occurs.

As a further example of the operation of the converter of Figure 2, the transformation in both directions of thev binary numbers Y1111 (cyclic) Vand 1010 (auth), Figure l(b), representing the quantityV l0, is illustrated in the following tabulation:

Input Control Output Pulse Pulse Pulse (Tcrm- (Terrn- (Terminal #1) inal #2) inal #3) ti. 1 0 l Cyclic to Arithmetical (Switch tu. 1 1 0 6 connected to Terminal 3). ts 1 0 1 in l. l t1 1 0 l Arithmetical to Cyclic (Switch tg 0 1 1 6 connected to Terminal l). ta. (l) (1J i4.

The converter shown in Figure 2 is for use with series pulse codes in which the pulses occur at equally spaced time intervals. In cases where the pulse code is of the type in which the various pulses occur simultaneously in parallelchannels the converters shown in Figures 3a and 3b may be used. Referring to Figure 3a, the converter shown is designed to handle a four place code and comprises parallel circuits a-a, b-b' c-c and d-d each corresponding to one place in the code. lf a binary pulse code in the cyclic system is applied to inputV terminals a, b, c and d there will appear at output terminals the corresponding binary pulse code in the arithof the high potential of its cathode to which the positive pulse was applied. 1f a positive pulse is applied to terminal 2 but no pulse is applied to terminal 1 a pulse is similarly produced at output terminal 3, the only difference being that in this case tube 7 instead of tube S conducts. lf positive pulses are simultaneously applied to both terminals 1 and 2 the increased cathode potential of each tube prevents either from conducting and no puise is produced at output terminal 3. And, finally, if i there is no signal applied to either terminals 1 or Z, both tubes 7 and S remain nonconductive and no output pulse is produced. The control circuit of Figure 4 therefore satisfies the performance requirements for the control circuits 5.

ln Figure 5 tubes 15 and 16 are normally biased to cutoff. When both tubes 15 and 16 are nonconductive the metical system. The transformation of the code in Figure l(a) from the cyclic to the arithmetical system is illustrated. The control circuits 5 of Figure 3a' have the same operational characteristics as the control circuit in Figure 2, namely: (l) a pulse on terminal 1 and no pulse on terminal 2 produces a pulse at terminal 3, (2) no pulse at terminal 1 and a pulse at terminal 2 produces a pulse at terminal 3, (3) a pulse at pulse at terminal 2 produces no pulse at terminal 3, and (4) no pulse at terminal 1 and no pulse at terminal 2 produces no pulse at terminal 3.

As already pointed out the transformation of each digit of the code from one system to the other depends only on the corresponding digit in the other code and the next higher order digit in the arithmetical code. The control signal applied to terminal 2 of circuit 5 must therefore always be derived from the arithmetical code signal. Since the arithmetical signal appears at the out-- put side of the converter in Figure 3a, the terminals 'Z are accordingly connected to the output side. If it is desired to modify the converter of Figure 3a to produce the reverse transformation, i. e., from the arithmetical to the cyclic system, it is only necessary to connect the terminals 2 to the input side of the converter where the arithmetical signal now appears. Such a modification is shown in Figure 3b. ln this figure the transformation from the arithmetical system to the cyclic system of the pulse code in Figure l(a) is illustrated.

Suitable arrangements of the control circuit 5 are Shown in Figures 4 and 5. Referring to Figure 4, the tubes 7 and 3 are biased to cut-olf by bias sources 1i) and 11. If a positive pulse is applied to terminal 1 but no pulse is applied to terminal 2 the cathode of tube 7 terminal 1 and a electrodes of tubes 17 and 18 are all at the same potential and therefore these tubes are nonconductive. If a positive pulse is applied to terminal 1 but no signal is applied to terminal 2, tube 15 conducts but tube 16 :remains nonconductive. Conduction in tube 15 lowers the cathode potential of tube 17 producing a negative pulse in the anode of this tube. This pulse is inverted by direct-coupled amplier tube 19 and is applied through cathode follower stage 20 to output terminal 3 as a positive pulse. Similarly, if a positive pulse is applied to terminal 2 but no signal is applied to terminal 1, an output pulse appears at terminal 3, the only difference being that in this case tubes 16 and 1S conduct instead of tubes 15 and 17. lf positive pulses are applied to both terminals 1 and 2, bothtubes 15 and 16 are conductive and the resulting drop in potential on the grids of tubes 17 and 18 maintains both of these tubes in a nonconductive state, so that no output pulse appears on terminal 3. Finally, in the absence of a signal on both terminals 1 and 2 both tubes 15 and 16 are biased to cut-rolf, and, as already explained, for this condition the electrodes of tubes 17 and 18 are all at the same potential so that no conduction occurs and there is no output pulse at terminal 3. Therefore, the circuit of Figure 5 also satises the performance requirements for control circuit 5.

What we claim is:

l. A converter for producing transformations between the cyclic and the arithmetical systems of binary numbers wherein said numbers appear as multiple place electrical binary codes in which each place is characterized by a digit signal consisting of the presence or absence of an electrical pulse and in which said digit signals occur simultaneously, said converter comprising a plurality of control circuits, equal in number to one less than the number of places in said multiple place code, said control circuits being identical and each having input, output and control terminals, means for applying each of, the digit signals with the exception of the highest order digit signal in an input electrical binary code in accordance with one of said binary systems to the input terminal of a corresponding one of said control circuits, means for applying said highest order digit signal to the control terminal of the control circuit to which the second highest order signal of said input electrical binary code is applied, means for connecting the control terminal of each of the remaining control circuits to a terminal of the next higher order control circuit other than the control terminal thereof, a plurality of output circuits equal in number to the number of places in said multiple place code in which the digit signals of the transformed electrical binary code are to appear, means for applying the highest order digit signal of said input electrical binary code to one of said output circuits, and means for connecting the remaining output circuits to the output terminals of said control circuits, each of said control circuits comprising first and second vacuum tubes each having a load resistor connected between its anode and a source of potential, means connecting the control circuit input terminal to the grid of said rst tube, means connecting the control circuit control terminal to the grid of said second tube, means biasing the grids of said first and second tubes beyond the cut-od point in the absence of signals thereon, third and fourth vacuum tubes, connecting the grid of said fourth tube to the anode or" said first tube and the cathode of said `fourth tube to a point intermediate the ends of the load resistor of said second tube, means connecting the grid of said third tube to the anode of said second tube and the cathode of said third tube to a point intermediate the ends of the load resistor of said rst tube, means connecting the anode circuits of said third and fourth tubes in parallel, and means coupling the control circuit output terminal to said parallel connected anode circuits.

2. A circuit for adding the binary digits 1 and 0 without carry-over to produce the sums 0-{-0=0, 0-{1=1, 1-}-0=1 and 1+1=0, said circuit comprising rst and second vacuum tubes each having an anode, a cathode and a control grid, means connecting the anode of each of said tubes through a load resistor to a source of positive potential, means connecting the cathodes of said tubes to a point of reference potential, third and fourth vacuum tubes each having an anode, a cathode and a grid, means connecting the grid of said fourth tube to the anode of said first tube and the cathode of said fourth tube to a point intermediate the ends of the load resistor of said second tube, means connecting the grid of said third tube to the anode of said second tube and the cathode of said third tube to a point intermediate the ends of the load resistor of said first tube, means connecting the anode circuits of said third and fourth tubes in parallel to an output circuit, means for applying a first input signal between the grid of said rst tube and said point of reference potential, means for applying a second electrical signal between the grid of said second tube and said point of reference potential, said electrical signals representing the digit 1 by a positive voltage and the digit 0 by a negative voltage, and means for biasing the grids of said first and second tubes beyond the cut-ofi point in the absence of signals thereon.

References Cited in the file of this patent UNITED STATES PATENTS 2,505,029 Carbrey Apr. 25, 1950 2,570,220 Earp Oct. 9, 1951 2,570,221 Earp Oct. 9, 1951 2,571,680 Carbrey Oct. 16, 1951 2,590,950 Eckert Apr. 1, 1952 2,596,199 Bennett May 13, 1952 2,600,744 Eckert June 17, 1952 2,632,104 Lakatos Mar. 17, 1953 

